[PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3 for s2idle

[Deucher, Alexander]

[AMD Public Use]

> -----Original Message-----
> From: Christoph Hellwig <hch at lst.de>
> Sent: Tuesday, May 25, 2021 2:21 AM
> To: Liang, Prike <Prike.Liang at amd.com>
> Cc: kbusch at kernel.org; axboe at fb.com; hch at lst.de; sagi at grimberg.me;
> linux-nvme at lists.infradead.org; Deucher, Alexander
> <Alexander.Deucher at amd.com>; S-k, Shyam-sundar <Shyam-sundar.S-
> k at amd.com>; Limonciello, Mario <Mario.Limonciello at amd.com>
> Subject: Re: [PATCH] nvme-pci: set some AMD PCIe downstream storage
> device to D3 for s2idle
> 
> On Tue, May 25, 2021 at 10:48:59AM +0800, Prike Liang wrote:
> > +#ifdef CONFIG_X86
> > +#include <asm/cpu_device_id.h>
> > +#endif
> >
> >  #include "trace.h"
> >  #include "nvme.h"
> > @@ -2828,6 +2831,16 @@ static unsigned long
> > check_vendor_combination_bug(struct pci_dev *pdev)  }
> >
> >  #ifdef CONFIG_ACPI
> > +
> > +#ifdef CONFIG_X86
> > +static const struct x86_cpu_id storage_d3_cpu_ids[] = {
> > +	X86_MATCH_VENDOR_FAM_MODEL(AMD, 25, 80, NULL),
> /*Cezanne*/
> > +	X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL),
> /*Renoir*/
> > +	X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104,
> NULL),/*Lucienne*/
> > +	{}
> > +};
> > +#endif
> 
> This is completely unacceptable.  The NVMe driver could not care less what
> CPU we on.  We need information from the PCI or power managment core
> on how broken the power management of the root port is, not this kind of
> crap in a low-level driver, with potentially many more needing the same kind
> of quirk in the future.

Hans,

Any ideas on how to handle this at that platform level?  We need to select the NVME_QUIRK_SIMPLE_SUSPEND flag on certain AMD platforms.  This is a platform firmware requirement.  It's not an NVME specific requirement, it's not a PCIe specific requirement, it's a platform specific requirement.  DMI matching doesn't really make sense because it affects all AMD platforms of a certain generation.

Thanks,

Alex