RDY bit clarification

[muthu crazy]

My concern is Reading RDY bit will trigger a MemRD PCIe transcation
which will add a delay for every command.
So it will affect the overall performance.

On 15 January 2018 at 07:27, Keith Busch <keith.busch at intel.com> wrote:
> On Sun, Jan 14, 2018 at 09:26:23AM +0530, muthu crazy wrote:
>> Why does linux nvme target code is checking for NVME_CSTS_RDY == 1
>> before submitting any IO commands to device. Is there any chance RDY
>> can go down after the controller initialization. It make sense if we
>> check for CFS instead of RDY.
>>
>> Isn't causing performance drop?
>
> I don't think it's for situations where RDY goest down on it's own, but
> for checking if a badly behaving host sends a command before respecting
> the proper state transitions.