[spi-nor] Macronix MX25L requires CR read opcode 0x15 (not 0x35)

[Miquel Raynal]

Hello,

On 22/08/2025 at 14:03:02 +02, Maarten Zanders <maarten at zanders.be> wrote:

> Hi all,
>
> On the Macronix MX25L12833F (ID 0xC22018) & others of this family/mfg,
> the CR (condition register) must be read with opcode 0x15. The driver
> currently uses 0x35, which the chip does not recognize.
>
> Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8934/MX25L12833F,%203V,%20128Mb,%20v1.0.pdf
> (p.27, RDCR).
>
> With 0x35 the data line floats and the driver reads CR as 0xFF
> (depending on previous state of the line or pull up/down). This value
> is then written back in spi_nor_write_16bit_sr_and_check(), setting CR
> to 0xFF. One consequence is flipping the OTP Top/Bottom protection
> bit, so from then on, locking the top block actually locks the bottom
> sector. This breaks bootloader updates (in my case) and similar flows.
>
> Possible fixes:
> - Make CR read opcode configurable per device.

FYI I just proposed a series which goes into that direction, with quite
a deep rework of the QER SFDP field handling. This rework allows on a
per chip basis to indicate:
- what are the status operations supported
- what are the opcodes for these operations

Link: https://lore.kernel.org/linux-mtd/20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com/T/#m0058d07965ba8c91a2438c5512e2b7b2693a6909

Thanks,
Miquèl