CYRS17B spi-nor flash support in ubi/ubifs

[Takahiro Kuwano]

Hello,

Infineon introduced a SPI-NOR flash chip named CYRS17B [1], which has untypical
features comparing to others SPI-NOR flash chips. I would like to ask you to
share your thoughts about possibility of UBI/UBIFS support this flash chip.

Features different from typical SPI-NOR flash are:
  #1 Inverted erase polarity. The data after erase is 0x00 instead of 0xFF.
  #2 Larger erase block size, 1MB (or 8MB). Typical SPI-NOR has 4KB to 256KB.
  #3 Larger program page size, 2KB. Typical SPI-NOR has 256B or 512B page.
  #4 Programming partial page initiates internal page erase.

Obviously, #1 is the biggest obstacle as UBI/UBIFS (and all other Flash File
Systems) are designed with an assumption, "0xFF as erase (blank) state".

#2 means there are less number of PEBs. I think this affects storage efficiency.

#3 and #4 seems not to be matter, if I configure UBI minimum IO size to 2KB to
avoid partial page programming.


I understand it isn't an easy task to update UBI/UBIFS for this Flash chip,
but opinions from experts would be really helpful.

Best Regards,
Takahiro Kuwano
 
[1] https://www.infineon.com/dgdl/Infineon-CYRS17B512_512_MB_64_MB_SERIAL_NOR_FLASH_SPI_QSPI_3-DataSheet-v07_00-EN.pdf?fileId=8ac78c8c8fc2dd9c01900eee733d45f3