[PATCH v13 2/4] mtd: spi-nor: spansion: Add support for volatile QE bit

[Tudor.Ambarus at microchip.com]

On 4/21/22 13:47, Takahiro Kuwano wrote:
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> On 4/21/2022 7:41 PM, Tudor.Ambarus at microchip.com wrote:
>> On 4/21/22 12:40, tkuw584924 at gmail.com wrote:
> [...]
>>> +/**
>>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
>>> + *                                      register.
>>> + * @nor:       pointer to a 'struct spi_nor'
>>> + *
>>> + * It is recommended to update volatile registers in the field application due
>>> + * to a risk of the non-volatile registers corruption by power interrupt. This
>>> + * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
>>> + * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
>>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
>>> + * also set during Flash power-up.
>>> + *
>>> + * Return: 0 on success, -errno otherwise.
>>> + */
>>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
>>> +{
>>> +       struct spi_mem_op op;
>>> +       u8 cfr1v_written;
>>> +       int ret;
>>> +
>>> +       op = (struct spi_mem_op)
>>> +               CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR1V,
>> nor->addr_width is 3, isn't it? can we use nor->addr_width instead of 3, please?
>>
> No, at the time this method is called, nor->addr_width is set to 4 by
> spi_nor_set_addr_width().

I see. Allow me some time to re-read this.