[PATCH v11 1/3] mtd: spi-nor: spansion: Add support for volatile QE bit

[Takahiro Kuwano]

On 4/19/2022 9:53 PM, Tudor.Ambarus at microchip.com wrote:
> On 4/18/22 08:41, tkuw584924 at gmail.com wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
>>
>> Some of Infineon chips support volatile version of configuration registers
>> and it is recommended to update volatile registers in the field application
>> due to a risk of the non-volatile registers corruption by power interrupt.
>>
>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
>> ---
>> Changes in v11:
>>   - Rebase on top of Tudor's series
>>     https://patchwork.ozlabs.org/project/linux-mtd/list/?series=294490
>>
>> Changes in v10:
>>   - Remove dependencies on other series
>>
>> Changes in v9:
>>   - Rename function per mwalle's series
>>
>> Changes in v8:
>>   - Use spi_nor_read/write_reg() functions
>>   - Use nor->bouncebuf instead of a variable on stack
>>
>> Changes in v7:
>>   - Add missing macro definitions in v6
>>
>> Changes in v6:
>>   - Remove multi die package support
>>
>> Changes in v5:
>>   - No change
>>
>> Changes in v4:
>>   - No change
>>
>> Changes in v3:
>>   - Add multi-die package parts support
>>
>>  drivers/mtd/spi-nor/spansion.c | 60 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 60 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
>> index 952db7af6932..6bcd25180af4 100644
>> --- a/drivers/mtd/spi-nor/spansion.c
>> +++ b/drivers/mtd/spi-nor/spansion.c
>> @@ -14,6 +14,8 @@
>>  #define SPINOR_OP_CLSR         0x30    /* Clear status register 1 */
>>  #define SPINOR_OP_RD_ANY_REG                   0x65    /* Read any register */
>>  #define SPINOR_OP_WR_ANY_REG                   0x71    /* Write any register */
>> +#define SPINOR_REG_CYPRESS_CFR1V               0x00800002
>> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN       BIT(1)  /* Quad Enable */
>>  #define SPINOR_REG_CYPRESS_CFR2V               0x00800003
>>  #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24  0xb
>>  #define SPINOR_REG_CYPRESS_CFR3V               0x00800004
>> @@ -117,6 +119,64 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
>>         return 0;
>>  }
>>
>> +/**
>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
>> + *                                      register.
>> + * @nor:       pointer to a 'struct spi_nor'
>> + *
>> + * It is recommended to update volatile registers in the field application due
>> + * to a risk of the non-volatile registers corruption by power interrupt. This
>> + * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
>> + * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
>> + * also set during Flash power-up.
>> + *
>> + * Return: 0 on success, -errno otherwise.
>> + */
>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
>> +{
>> +       struct spi_mem_op op;
>> +       u32 reg_addr = SPINOR_REG_CYPRESS_CFR1V;
>> +       u8 cfr1v_written;
>> +       int ret;
>> +
>> +       op = (struct spi_mem_op)
>> +               CYPRESS_NOR_RD_ANY_REG_OP(nor->addr_width, reg_addr,
>> +                                         nor->bouncebuf);
>> +       ret = spi_nor_read_reg(nor, &op, SNOR_PROTO_1_1_1);
>> +       if (ret)
>> +               return ret;
>> +
>> +       if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
>> +               return 0;
>> +
>> +       /* Update the Quad Enable bit. */
>> +       nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
>> +       op = (struct spi_mem_op)
>> +               CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_width, reg_addr, 1,
>> +                                         nor->bouncebuf);
>> +       ret = spi_nor_write_reg(nor, &op, SNOR_PROTO_1_1_1);
>> +       if (ret)
>> +               return ret;
> 
> should you call spi_nor_wait_until_ready() here?
> 
No. For volatile register write, it finishes immediately and the device
does not get in busy state. Reading back and verifying the register bit
is good enough.

>> +
>> +       cfr1v_written = nor->bouncebuf[0];
>> +
>> +       /* Read back and check it. */
>> +       op = (struct spi_mem_op)
>> +               CYPRESS_NOR_RD_ANY_REG_OP(nor->addr_width, reg_addr,
>> +                                         nor->bouncebuf);
>> +       ret = spi_nor_read_reg(nor, &op, SNOR_PROTO_1_1_1);
>> +       if (ret)
>> +               return ret;
>> +
>> +       if (nor->bouncebuf[0] != cfr1v_written) {
>> +               dev_err(nor->dev, "CFR1: Read back test failed\n");
>> +               return -EIO;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>>  /**
>>   * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
>>   * @nor:               pointer to a 'struct spi_nor'
>> --
>> 2.25.1
>>
>