[PATCH] mtd: spinand: Add support for GigaDevice GD5F4GQ4xC
gch981213 at gmail.com
Sun Aug 16 23:38:42 EDT 2020
On Sun, Aug 16, 2020 at 9:36 PM Hauke Mehrtens <hauke at hauke-m.de> wrote:
> Tbe GigaDevice SPI NAND chips have a QE bit and it has to be set to make
> the quad operations work accordingly to the datasheets.
You are right. I copied code from winbond.c back then. I don't have any
qspi capable boards to test it and didn't notice this QE bit and the incorrect
QUADIO instruction you mentioned below. Sorry for that :(
> Does the flag SPINAND_HAS_QE_BIT mean that the QE bit has to be set to
> activate quad operations and when we do not have this flag set it means
> quad works also without activating it?
> Does Linux assume that all SPI NAND flash chips support quad mode well?
Quad mode support is indicated in SPINAND_OP_VARIANTS. spi nand core
will match controller capability against defined supported instructions, and
use the first one supported by both chip and controller.
> Even when I add SPINAND_HAS_QE_BIT, quad mode is still not working for
> me with this chip.
> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP looks wrong to me, currently it
> looks like this:
> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
> but it should be like this:
> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
> The operation only has 1 dummy byte and not 2.
> I can send a patch for this, if you think it is correct.
Please do so.
I've just checked datasheets of GD5FxGQ4xA/E currently supported and
they all use only one dummy byte in quadio op.
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