[PATCH] mtd: spinand: Add support for GigaDevice GD5F4GQ4xC

[Hauke Mehrtens]

On 8/15/20 7:27 PM, Hauke Mehrtens wrote:
> This adds support for the following 4GiB chips:
> GD5F4GQ4RCYIG 1.8V
> GD5F4GQ4UCYIG 3.3V
> 
> The datasheet can be found here:
> https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf
> 
> The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination
> Technologies Creator Ci40 (Marduk), the 1.8V version was not tested.
> 
> This device only works in single SPI mode and not in dual or quad mode
> for me on this board.
> 
> Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
> ---
>  drivers/mtd/nand/spi/gigadevice.c | 49 +++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
> index d219c970042a..96625e2bdf1e 100644
> --- a/drivers/mtd/nand/spi/gigadevice.c
> +++ b/drivers/mtd/nand/spi/gigadevice.c
> @@ -132,6 +132,35 @@ static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
.....
>  static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
>  					u8 status)
>  {
> @@ -225,6 +254,26 @@ static const struct spinand_info gigadevice_spinand_table[] = {
>  		     0,
>  		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
>  				     gd5fxgq4xa_ecc_get_status)),
> +	SPINAND_INFO("GD5F4GQ4RC",
> +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68),
> +		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> +		     NAND_ECCREQ(8, 512),
> +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
> +					      &write_cache_variants,
> +					      &update_cache_variants),
> +		     0,

Tbe GigaDevice SPI NAND chips have a QE bit and it has to be set to make
the quad operations work accordingly to the datasheets.
Does the flag SPINAND_HAS_QE_BIT mean that the QE bit has to be set to
activate quad operations and when we do not have this flag set it means
quad works also without activating it?

Does Linux assume that all SPI NAND flash chips support quad mode well?

Even when I add SPINAND_HAS_QE_BIT, quad mode is still not working for
me with this chip.

SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP looks wrong to me, currently it
looks like this:
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
but it should be like this:
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
The operation only has 1 dummy byte and not 2.
I can send a patch for this, if you think it is correct.

Hauke

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