[RFC PATCH 0/5] RFC for Zynq QSPI

[Naga Sureshkumar Relli]

Hi Marek,

Thanks for reviewing the patch.

> -----Original Message-----
> From: Marek Vasut [mailto:marek.vasut at gmail.com]
> Sent: Friday, March 23, 2018 6:22 PM
> To: Naga Sureshkumar Relli <nagasure at xilinx.com>;
> cyrille.pitchen at wedev4u.fr; dwmw2 at infradead.org;
> computersforpeace at gmail.com; boris.brezillon at free-electrons.com
> Cc: linux-mtd at lists.infradead.org; Naga Sureshkumar Relli
> <nagasure at xilinx.com>
> Subject: Re: [RFC PATCH 0/5] RFC for Zynq QSPI
> 
> On 03/23/2018 01:21 PM, Naga Sureshkumar Relli wrote:
> > Xilinx Zynq uses a QSPI controller that is based on the Cadence SPI IP.
> 
> Don't we have a CQSPI driver already ? Why is this adding a new one ?
Zynq QSPI Controller is designed by using Cadence SPI IP core in order to add multi bit IO capability.
The modified core is Zynq QSPI Controller core. Both are different.
> 
> --
> Best regards,
> Marek Vasut

Thanks,
Naga Sureshkumar Relli.