[PATCH 00/11] Introduction to SPI NAND framework

[Peter Pan]

On Tue, Feb 21, 2017 at 4:11 PM, Peter Pan <peterpansjtu at gmail.com> wrote:
> Hi Richard,
>
>
> On Tue, Feb 21, 2017 at 4:05 PM, Richard Weinberger <richard at nod.at> wrote:
>> Peter,
>>
>> Am 21.02.2017 um 08:59 schrieb Peter Pan:
>>> This serie introductes a SPI NAND framework.
>>> SPI NAND is a new NAND family device with SPI protocol as
>>> its interface. And its command set is totally different
>>> with parallel NAND.
>>>
>>> Our first attempt was more than 2 years ago[1]. At that
>>> time, I didn't make BBT shareable and there were too many
>>> duplicate code with parallel NAND, so that serie stoped.
>>> But the discussion never stops. Now Boris has a plan to
>>> make a generic NAND framework which can be shared with
>>> both parallel and SPI NAND. Now the first step of the
>>> new generic NAND framework is finished. And it is waiting
>>> for a user. After discussion with Boris. We both think it's
>>> time to rebuild SPI NAND framework based on the new NAND
>>> framework and send out for reviewing.
>>>
>>> This serie is based on Boris's nand/generic branch[2], which
>>> is on 4.9-rc1. In this serie, BBT code is totally shared.
>>> Of course SPI NAND can share more code with parallel, this
>>> requires to put more in new NAND core (now only BBT included).
>>> I'd like to send this serie out first, then we can decide
>>> which part should be in new NAND core.
>>>
>>> This serie only supports basic SPI NAND features and uses
>>> generic spi controller for data transfer, on-die ECC for data
>>> correction. Support advanced features and specific SPI NAND
>>> controller with hardware ECC is the next step.
>>
>> Can you please share on which SPI NAND chips this got tested?
>
> Sorry for missing this part in cover letter... This series is tested on
> Xilinx Zedboard with Micron MT29F2G01AAAED SPI NAND chip.

Sorry for mistake, the chip should be MT29F2G01ABAGDSF

Thanks,
Peter Pan