brcmnand (iproc): bitflips and ECC errors due to ignored ECC config

[Brian Norris]

On Mon, Feb 08, 2016 at 02:15:16PM -0500, Kamal Dasu wrote:
> When SECTOR_SIZE = 512B, SPARE_AREA_SIZE  = 16, ECC_LEVEL = 15 enables
> 1-bit Hamming ECC protection. So the ecc_level field is the SoC
> internal representation for 1-bit hamming. If you mean by "removing
> handling" you made strength=ecc_level=1, then you are now using 1-bit
> BCH.

It kinda sounds like Rafal is suggesting this product uses 1-bit BCH.
I didn't even remember such a thing existed on this controller.
Unfortunately, we don't really have a way to clearly differentiate 1-bit
Hamming and 1-bit BCH in DT, do we? Both could equally well be described
by:

	nand-ecc-strength = <1>;
	nand-ecc-step-size = <512>;

Maybe we need a custom BRCM property?

Brian