WP# line on flash chip?

[Steve deRosier]

Our flash chip has an active-low write-protect line controlled via a
GPIO. It's out-of-band of everything, the interface still has CS and
other normal signals and those are connected to the NAND controller
pins on our controller.  This pin isn't controlled by the controller,
it's a GPIO activated pin. It's also out-of-band of the various LOCK
commands that can be sent.

The datasheet basically says it locks down the chip so that random
data on the bus doesn't cause erase or programs.  Micron is telling us
that we really should keep it asserted and only deassert it when we
want to erase/write the device.  Right now, we deassert it shortly
after boot.

I can't find any way to add this pin to our device tree, nor do I see
any evidence for support in either our atmel_nand driver or in
higher-level MTD stuff like nand_base.

Does the support for this exist and am I simply missing finding it, or
is it not there at all (expected)?

Assuming it's not there, and assuming I actually add it, is this a
feature that the MTD maintainers would allow to go upstream? I'm
assuming it's not a unique feature to this chip and that other chips
may have it.

Thanks,
- Steve