[PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
maxime.ripard at free-electrons.com
Mon Feb 16 08:49:20 PST 2015
On Mon, Feb 16, 2015 at 10:35:50AM -0300, Ezequiel Garcia wrote:
> On 02/16/2015 09:51 AM, Maxime Ripard wrote:
> > The NDDB register holds the data that are needed by the read and write
> > commands.
> > However, during a read PIO access, the datasheet specifies that after each 32
> > bits read in that register, when BCH is enabled, we have to make sure that the
> > RDDREQ bit is set in the NDSR register.
> Typo s/32 bits/32 bytes
Good catch, thanks!
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 819 bytes
Desc: Digital signature
More information about the linux-mtd