[PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

Ezequiel Garcia ezequiel.garcia at free-electrons.com
Mon Feb 16 05:35:50 PST 2015

On 02/16/2015 09:51 AM, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.

Typo s/32 bits/32 bytes

Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering

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