[PATCH 1/1 v2] driver:mtd:spi-nor: Add Micron quad I/O support

[bpqw]

>> For Micron spi norflash,you can enable Quad spi transfer by clear 
>> EVCR(Enhanced Volatile Configuration Register) Quad I/O protocol bit.
>
>OK, this information is nice and all, but what does this patch do? I can't learn this information from the commit message as it is, can I ? 
>And , the purpose of the commit message is exactly to summarize the change the patch implements.


you don't understand what purpose of this patch! just as subject and commit message described,
it is for enable Micron Quad spi transfer mode.do you read the spi-nor.c file? please pay attention
to the set_quad_mode() function.by the way,I can add more commit message for it,but I think
it is redundant,don't need.

>> +static int micron_quad_enable(struct spi_nor *nor) {
>> +	int ret, val;
>> +
>> +	ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
>> +	if (ret < 0) {
>> +		dev_err(nor->dev, "error %d reading EVCR\n", ret);
>> +		return -EINVAL;
>> +	}
>> +
>> +	write_enable(nor);
>> +
>> +	/* set EVCR ,enable quad I/O */
>> +	nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
>> +	ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
>> +	if (ret < 0) {
>> +		dev_err(nor->dev,
>> +			"error while writing EVCR register\n");
>> +		return -EINVAL;

>Why not just "return ret;" ?
>[...]

Ok,this is good,I will modify it in the next patch version.thanks.