Page corruption when writing non-sequential pages in an MLC NAND eraseblock

[Romain Izard]

2013/10/3 Avery Pennarun <apenwarr at gmail.com>:
> On Thu, Oct 3, 2013 at 12:40 AM, Ricard Wanderlof
> <ricard.wanderlof at axis.com> wrote:
>> Just because they place the constraint on the user that the pages must be
>> written in order doesn't mean that the device necessarily will malfunction
>> if the user violates this. It just means that the designers have the freedom
>> to introduce dependencies between the page writes if it makes the design
>> easier/better/possible/whatever. It could very well be that for a given
>> flash it is possible to do some writes out of order, but to avoid a) tying
>> down the actual possibilities for a given flash and b) complicating the
>> facts for the user they just specify that 'page writes must be executed in
>> order'.
>>
>> I must admit I wasn't aware of this fact either, but I have no hands-on
>> experience with MLC flashes on the other hand.
>
> It seems rather under-documented to me, and I wouldn't be overly
> surprised if it's not so much "standard behaviour" as "behaviour some
> chip makers decided they could get away with based on usage patterns."
>  But ok.
>

It's right there in the datasheet for both MLC manufacturers I have worked with.
And it seems that even SLC flash with large blocks [1] can also have the
same constraint.

There is very interesting technical presentation from Micron [2] that explains
all the issues with NAND flash, and that states that the write order
is necessary
to reduce the 'program disturb' issues.

[1] http://permalink.gmane.org/gmane.linux.drivers.mtd/20182
[2] https://www.micron.com/~/media/Documents/Products/Presentation/flash_mem_summit_jcooke_inconvenient_truths_nand.pdf

Regards,
-- 
Romain Izard