Per-partition NAND ECC?

[Peter Barada]

On the OMAP3 parts the bootrom has a hard requirement of using 1-bit
Hamming ECC to read the 2nd stage bootloader(x-loader / SPL) out of the
first four blocks of NAND.  The Micron MT29C4G48MAZAPAKQ5 PoP part we're
using requires 4-bit ECC for all the other NAND blocks to maintain an
acceptable UBER.

Currently this wasn't a problem since I could use u-boot to update the
2nd stage bootloader. I now have a need to be able to update the 2nd
stage bootloader from Linux only so I need the ability to write/read
pages in a NAND partition with a different ECC method than that
specified over the device.  I think it would be more elegant to solve
this by allowing partition entry/mtdparts to specify its ECC
methodology, track that as part of the MTD device down into the nand
driver, and switch ECC methods/entrypoints as it changes.

Does anyone have suggestions on how to best approach this?

Thanks in advance!

-- 
Peter Barada
peter.barada at gmail.com