how to support 4096+224 page size with plat_nand ?

[Brian Norris]

On Mon, Mar 19, 2012 at 7:40 AM, STOTTS Timothy
<timothy.stotts at transport.alstom.com> wrote:
> How can I determine a valid ECC layout for OOB size of 224? A copy-and-paste of a layout found on the Internet resulted in the driver marking all blocks as "bad block" on the NAND Flash. (We have additional chips to work with.) My chip uses software ECC. Does it require BCH?

This depends on your ECC level needed. If you stick with
NAND_ECC_SOFT, then (I think) you get 1-bit (Hamming) ECC. You can
probably just reuse the nand_oob_128 layout for 224. If you need
higher ECC correction, you might need BCH and would switch to
NAND_ECC_SOFT_BCH which I think calculates its own layout.

BTW, BCH is simply an algorithm used for Error Correction. It's
commonly used for anything higher than 1-bit ECC. I'm not very
familiar with software BCH (or software ECC in general).

So you might try just using nand_oob_128 layout by modifying the
`switch (mtd->oobsize) ...' logic. BCH would be a fallback option, or
if you need higher correction.

> My datasheet does not specify ECC as number of OOB bytes per 4096 bytes, as such, but rather as a number of bits per a smaller number of bytes. Does that matter?

That's typical. Usually it's measured across a 512-byte or 1024-byte
sector (sometimes adding OOB, giving odd sizes like 512+16=528, or
512+28=540, etc.).

Brian