expect bit flip within endurance if ECC is required?

[Peter Barada]

On 08/02/2012 11:24 AM, peterlingoal wrote:
> Hi all,
>
> I have some questions about minimum ECC and NAND endurance, please help me here:
>
> My understanding of endurance is that a NAND and survive the number of
> cycles of erase/write/read before any error occurs. But I am not clear
> about the definition of error, is it correctable error (bit flip less
> than minimum ECC) or uncorrectable error (more than minimum ECC)? For
> e.g. if a NAND with endurance of 100,000 cycles and requires minimum
> 4bit ECC, shall I expect bit flipping (but less than 4 bits) within
> the 100,000 cycles?
>
> If my understand is correct, does it mean that the chip with same
> endurance but higher minimum ECC requirement is more likely to have
> bit flipping faster than the chip with same endurance but less minimum
> ECC?
Yes.  the number of bits of ECC implies the rate of correctable errors -
more bits of ECC imply more bits per read that can flip (and are
corrected by the ECC).  Older large-geometry SCL nand parts wouldn't
show a single bit flip until that block is near its end of life whereas
newer small-geometry SLC/MLC show bit flips much more often - the CBER
(correctable bit error rate) is much higher with newer NAND devices.

The strength of the ECC is such that the UBER (uncorrectable bit error)
can be held low - 10E-15 or so over the life of the device.  Note that
to maintain retention and usable UBER, chip manufacturers define
temperature ranges, and not only retiring blocks after a maximum number
of erasures, but also require "refreshing" blocks (garbage collect valid
data from the block into another) after a set number of reads from a
block - across power cycles.

-- 
Peter Barada
peter.barada at gmail.com