expect bit flip within endurance if ECC is required?

[peterlingoal]

Hi all,

I have some questions about minimum ECC and NAND endurance, please help me here:

My understanding of endurance is that a NAND and survive the number of
cycles of erase/write/read before any error occurs. But I am not clear
about the definition of error, is it correctable error (bit flip less
than minimum ECC) or uncorrectable error (more than minimum ECC)? For
e.g. if a NAND with endurance of 100,000 cycles and requires minimum
4bit ECC, shall I expect bit flipping (but less than 4 bits) within
the 100,000 cycles?

If my understand is correct, does it mean that the chip with same
endurance but higher minimum ECC requirement is more likely to have
bit flipping faster than the chip with same endurance but less minimum
ECC?

thanks,
Peter