UBIFS recovery fails

[Ricard Wanderlof]

>> This would be true, if you could assume that a page reading failure always
>> occurs after a previous read on the same page reports an ecc correction.
>> But this is not the case: we had several unstable pages going from 0 bitflips
>> (perfect read) to 2 bitflips (failed read). No way to detect any failure, no
>> way to scrub data before it's too late.
>> And the answer from the manufacturer was: you should not use any partially
>> programmed/erased pages anyway, those should be cleaned up after recovering
>> from a power failure.
>
> This should not append if you use recommended ECC bits count defined by the NAND part.
> Can you verify that, because 1 bit ECC for each 512 byte is only recommended by older
> SLC flash which are pretty stable.  Newer NAND need more ECC bits, which can be
> addressed by using BCH parities.

I would think that the manufacturers ECC recommendation is only valid if 
the page is properly programmed. If a power failure occurs during the 
writing of a page, it has not been programmed according to the 
manufacturer's specification, hence it is not properly programmed, and no 
assumptions can be made as to the validity of the data.

I remember a time in the dark old days of EPROMs, when I programmed an 
EPROM with too low a programming voltage (Vpp) - like 21V when the device 
required 25V. It verified correctly in the EPROM programmer, but when 
installed in the system for which it was intended, the data read out was 
faulty.

That said, it seems to me that power failure during write causing 
excessive bitflips would be a problem with any flash, not just MLC or 
modern "unstable" SLC. Ivan, you said you've only seen it with modern 
flashes, not older SLC ?

/Ricard
-- 
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30