UBIFS Corrupt during power failure
jamie at shareable.org
Wed Jul 15 16:52:17 EDT 2009
Eric Holmberg wrote:
> I verified with Spansion that the embedded erase algorithm first clears
> all 1's to 0's before erasing the bits to charge them back up to 1.
I suspect that's quite common for NOR cells.
Here's a question: Does it ever happen for NAND cells? Does the UBIFS
code assume that NAND erase only _ever_ converts 0 bits to 1 bits,
never 1 bits to 0 bits temporarily?
> Essentially, the contents of the PEB are indeterminate between the start
> and completion of an erase cycle. The erase algorithm isn't
> configurable, so we are stuck with this behavior.
> > > This patch seems to fix the UBI issues Eric and me observed
> > (issue N2).
> > > I'll test the patch for few days, but I couldn't see any
> > problem so far.
> The patch to write to the header is a great solution and I think it's
> the only possible solution. Performance should be fine, since the
> 4-byte write should only take about 0.5ms which is insignificant
> compared to a typical PEB erase time of 700ms.
I agree with the solution.
Can the same problem arise with NAND? I don't mean "every NAND we
tested", but NAND in general? Is it correct to assume they never
convert 1 bits to 0 bits temporarily during the erase cycle, and
should the UBIFS code write something to the PEB which invalidates the
header to ensure this cannot result in the same problems we've seen
You can't necessarily overwrite the header with NAND, but you might be
able to write elsewhere to say "this PEB is undergoing erase and is
> I will run 4 boards through torture tests starting tonight and let you
> know later this week! Based upon the errors that I've seen and looking
> at the patch, I think that should solve the problem.
> Great work guys!
I've been holding off trying UBI on NOR. Now it's looking more tempting :-)
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