[PATCH 4/4 v2] mtd/powerpc: Describe multiple "reg" tuples usage
Grant Likely
grant.likely at secretlab.ca
Sun Apr 12 02:05:53 EDT 2009
On Tue, Apr 7, 2009 at 2:39 AM, Stefan Roese <sr at denx.de> wrote:
> Signed-off-by: Stefan Roese <sr at denx.de>
> CC: Grant Likely <grant.likely at secretlab.ca>
> ---
> Documentation/powerpc/dts-bindings/mtd-physmap.txt | 20 +++++++++++++++++++-
> 1 files changed, 19 insertions(+), 1 deletions(-)
>
> diff --git a/Documentation/powerpc/dts-bindings/mtd-physmap.txt b/Documentation/powerpc/dts-bindings/mtd-physmap.txt
> index ab1115e..a3fa9e0 100644
> --- a/Documentation/powerpc/dts-bindings/mtd-physmap.txt
> +++ b/Documentation/powerpc/dts-bindings/mtd-physmap.txt
> @@ -5,7 +5,10 @@ file systems on embedded devices.
>
> - compatible : should contain the specific model of flash chip(s)
> used, if known, followed by either "cfi-flash" or "jedec-flash"
> - - reg : Address range of the flash chip
> + - reg : Address range(s) of the flash chip(s)
> + It's possible to (optionally) define multiple "reg" tuples so that the
> + Intel P30 48F4400 chip which consists internally of 2 non-identical
> + NOR chips on one die can also be supported.
This isn't a P30 48F4400 specific feature, even if it is the only
current user. This description works for any arrangement of multiple
NOR chips. I isn't really appropriate to mention the P30 in this way
and it should be more generic.
> - bank-width : Width (in bytes) of the flash bank. Equal to the
> device width times the number of interleaved chips.
> - #address-cells, #size-cells : Must be present if the flash has
> @@ -58,3 +61,18 @@ Example:
> read-only;
> };
> };
> +
> +Here an example with multiple "reg" tuples (e.g. Intel P30):
However, it is completely appropriate to mention P30 here because it
is in the context of an example.
> +
> + flash at f0000000,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
For best practice, compatible should also specify the exact chip in this case.
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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