Support of removable MTD devices and other advanced features (follow-up from lkml)

[Jamie Lokier]

Jörn Engel wrote:
> > That seems like it would cause uneven wear-levelling in some
> > situations.  Specifically, each time you need to erase a block which
> > has not been completely written, because you need to write a
> > contiguous record larger than the remaining space.
> > 
> > I don't know it was a physical requirement of some chips, thanks for
> > clarifying.
> 
> The "progressive" limitation only concerns writes _within_ eraseblocks.
> It has no impact on wear leveling.

I understood that.

I mean that progressive writing may cause more wear towards the
beginning of _each_ eraseblock, because you'll write more often at the
start of each eraseblock than the end.  That's if wear is at all a
function of writes, and not solely erase operations.

There's another curious thought: do individual flash bit cells wear
out more quickly when written to "0" or left at "1"?  I doubt it, but
if it did make a difference, it would make a case for xoring data with
predictable pseudo-random bits.

-- Jamie