anemo at mba.ocn.ne.jp
Tue Feb 19 10:40:52 EST 2008
On Mon, 18 Feb 2008 17:02:40 +0100 (CET), Ricard Wanderlof <ricard.wanderlof at axis.com> wrote:
> > Though it seems work fine as is, I wonder keeping chipselect signal
> > low all the time is normal.
> I think it is necessary for some flash chips. E.g. to erase, one cannot
> just issue an erase command and make NCE go inactive, as making NCE go
> inactive stops the erase procedure until asserted again.
Do you mean busy period between erase command and read-status command?
The nand framework does not try to inactivte NCE for that period.
I'm wondering why at91_nand keeps NCE active after all bus operation
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