[PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings
Sergei Shtylyov
sshtylyov at ru.mvista.com
Tue Apr 1 09:04:18 EDT 2008
Laurent Pinchart wrote:
>>>On Monday 31 March 2008 19:06, Sergei Shtylyov wrote:
>>>>> p) Freescale Synchronous Serial Interface
>>>>>- q) USB EHCI controllers
>>>>>+ q) USB EHCI controllers
>>>>>+ r) Memory-mapped RAM & ROM
>>>> Memory-mapped RA/RO Memory again? Should better drop this. :-)
>>>You're quite picky, aren't you ? :-)
>>>I suppose "Memory-mapped RA & RO" won't be accepted, so what about "Auxiliary
>>>RAM & ROM" ?
>>Direct-mapped?
> Fine with me. Sergei ?
I agree. The only thing that somewhat worries me it that it will have no
"compatible" prop...
WBR, Sergei
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