Does mtd support two-plane page program for nand flash?
kmpark at infradead.org
Fri Mar 9 03:37:17 EST 2007
> ext Jörn Engel wrote:
> > On Wed, 7 March 2007 14:57:02 +0800, falls huang wrote:
> >> AFAIK , the samsung's nand flash
> >> support two-plane page program. For example: The K9LAG08U0M is
> >> arranged in four 4Gb memory planes.Each plane contains
> 2,048 blocks
> >> and 2112 byte page registers. This allows it to perform
> >> page program and block erase by selecting one page or
> block from each
> >> plane. ( refer to the datasheet of K9LAG08U0M)
> > Interesting. I was wondering when devices like this would show up.
> > Do you have a spec for those chips?
NAND: There are also 512B 4-plane and 2KB 4-plane
> OneNAND DDP does this too (google: onenand "2x program")
> I presume the possibility exists to have the driver pretend
> that the page size is twice as large and there are half as
> many erase blocks.
> It would have to map the addressses accordingly - and
> everything else would have to be willing to accept a 4KiB
> page with 8 subpages and 128 bytes of oob.
In my understand, If we use the 2x program, we assume physical 2 blcoks to logical 1 block in JFFS2 or others.
Since "2x program" writes each bufferram to each block instead of same block.
So if we assume 4KiB page, we programe block 0, page 0 and block 1, page 0, In my opinion, it's not fit for JFFS2.
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