Limited support of NAND features in MTD.

[Alexander Belyakov]

On Dec 18, 2007 5:23 PM, Jörn Engel <joern at logfs.org> wrote:
>
> What does cached read do?
>

Some NAND chips have PAGE READ CACHE MODE operation
that uses the cache register to read data. The basic idea is as
follows: a page of data is transferred from the Flash array to the
data register and moved to the cache register when the PAGE READ
CACHE MODE command is issued. After this command is issued, data can
be clocked out of the cache register through the NAND Flash interface,
while the next page of data is simultaneously moved from the Flash
array to the data register.

So PAGE READ CACHE MODE operation saves time to read
each page. Pages must be sequentially read one by one without
interruption. The more pages read sequentially, the more read performance
improvement is (with saturation, of course).

Alexander