FPGA NAND Interface tips

[Russ Dill]

> Also, when writing/reading to a single address, the 80200 will not
> burst, and round trip time is horrid, especially when talking to IO
> devices. Would a FIFO with a 32 byte interface be a good solution to
> this? maybe with 16 entries (512 bytes)? I realize that DMA would be
> more ideal, but a fifo seems like it might be simplier.

quick rethink on that portion, the input to the fifo would be 8 bytes
(80200 has a 64 bit data interface)