FPGA NAND Interface tips

Russ Dill russ.dill at gmail.com
Fri Feb 24 00:07:36 EST 2006

I'm providing some input on the NAND wire up, and FPGA design on a new
board (80200 + FPGA).  I'm currently using rtc_from4.c and s3c2410.c
as examples.

So I'm thinking the following for a basic setup:

reed solomon encoder
Bit in the FPGA to reset the reed solomon encoder
place in the FPGA to read out rs codes from last written/read block
CLE/ALE as address lines
Read/Busy connected as gpio/interrupt (multiple chips connect to multiple lines)

Also, when writing/reading to a single address, the 80200 will not
burst, and round trip time is horrid, especially when talking to IO
devices. Would a FIFO with a 32 byte interface be a good solution to
this? maybe with 16 entries (512 bytes)? I realize that DMA would be
more ideal, but a fifo seems like it might be simplier.

Does anyone have any paticular pet peeves when dealing with their NAND

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