Questions about NAND (double)bit errors

[Wolfgang Mües]

Hello Charles,

Charles Manning wrote:
> * YAFFS is very conservative on dealing with ECC failures. YAFFS retires a
> block if one ECC failure is seen. JFFS2, IIRC allows five of so failure
> before retiring a block. The Toshiba folk have told me that if a block is
> going bad, it is most likely to start displaying recoverable 1-bit errors
> before displaying non-recoverable multi-bit errors. Thus, YAFFS will
> potentially perform differently in this area.

About bad block detection: what is your oppinion about partitioning the flash 
(the programs in a read-only partition, the data in r/w).

How about detection of ECC errors in read only partitions?

> One important factor, IMHO, is how you handle the write protect pin on the
> NAND. Some people tie the WP to the power supply failure flag. IMHO this is
> a bad thing to do since it can cause incomplete writes to happen if the wp
> is asserted during a write or erase cycle.

I have checked this.

WP is tied to VCC, and VCC is stable at least 500ms after a power fail detect.

best regards
-- 
Wolfgang Muees                    Vor den Grashoefen 1
Auerswald GmbH & Co. KG       	  D-38162 Cremlingen
Hardware Development              Germany
Tel +49 5306 9219 0               Fax +49 5306 9219 94