Questions about NAND (double)bit errors

[Wolfgang Mües]

Hello Charles,

thank you for sharing your experience...

You wrote:
> If you have not already done so, read the Toshiba NAND flash application
> guide:

Yes, I have.

> I have done a few accelerated lifetime tests that have gone very well. In
> one test (run once on 512byte page devices and once on 2k page devices) I
> wrote, read back and verified over 120Gbytes of data to the fs without a
> single bit betting lost.

You mean, without a single error correction? Or do you mean that ECC has done 
its job?

Regarding the 120 GBytes: How many times was each block written/erased? Have 
you reached the specified lifetime of the flash?

> * YAFFS is very conservative on dealing with ECC failures. YAFFS retires a
> block if one ECC failure is seen. JFFS2, IIRC allows five of so failure
> before retiring a block. The Toshiba folk have told me that if a block is
> going bad, it is most likely to start displaying recoverable 1-bit errors
> before displaying non-recoverable multi-bit errors.

This is a valuable information not found in other resources.

> Still, I think those reliability differences, at the flash level, are more
> than likely theoretical noise and are unlikely to be material in the real
> world.

Hmmmm... can you come and tell this to my boss ;-)

> One important factor, IMHO, is how you handle the write protect pin on the
> NAND. Some people tie the WP to the power supply failure flag. IMHO this is
> a bad thing to do since it can cause incomplete writes to happen if the wp
> is asserted during a write or erase cycle.

I will check this.

best regards

-- 
Wolfgang Muees                    Vor den Grashoefen 1
Auerswald GmbH & Co. KG       	  D-38162 Cremlingen
Hardware Development              Germany
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