[PATCH] NAND: Fix NAND ECC errors on AMD Au1550

Sergei Shtylylov sshtylyov at ru.mvista.com
Sat Oct 29 16:44:07 EDT 2005


          (This is a follow-up to the older thread:

          Reintroducing the problem: the static bus controller fails to keep
-CE asserted during chip ready delay on read commands (the NAND chip being
used requires this). So, the current driver allows nand_base.c to drive -CE
manually (during the whole sector read). When the PCMCIA driver is enabled
however, occasionally the ECC errors occur on NAND reads. This happens because
PCMCIA driver polls sockets periodically and reads one of the board's
control/status regs (BCSRs) which are accessible via the same static bus
as the NAND flash using the different chip select (and the NOR flash is
accessible the same way), so as the NAND driver forces NAND chip select
asserted and the -RE signal is shared, there's a contention on the static
bus when BCSR or NOR flash is read while we're reading from NAND.
          So, we either can't keep interrupts enabled during the whole NAND
sector read (which is hardly acceptable), or have to implement some
interlocking scheme between multiple drivers (which is painful, and makes
me shudder :-).
          There's a third way which proved to work: to force -CE asserted only
while we're waiting for NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microsecs (according to Toshiba
TC58DVM92A1FT00 flash chip datasheet). So, here's the initial patch which
I'm hoping to have made looking more decently...

WBR, Sergei

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