[PATCH] MTD NAND: Fix ECC errors in au1550nd.c

Thomas Gleixner tglx at linutronix.de
Mon Oct 3 19:10:10 EDT 2005

On Mon, 2005-10-03 at 17:22 +0400, Vitaly Bordug wrote:
> David,
> This patch fixes ECC errors by automatic CS assertion in the driver.
> We still use manual drive of CS only during READ CYCLE and READ OOB
> CYCLE, while overriding CS right after third address byte latch and
> finishing override after first data byte read.
>   From the Nand read page cycle timings (Toshiba Datasheet) 

Come on. I know those data sheets quite well and there is more than one.
Which chip type (Manufacturer part Nr) are you using ? 

> - we have to
> keep CS active from third address byte latch to the end of the cycle

Thats a known issue and the controller has worked with those chips

> It seems that static controller drives CS to low after fourth address
> byte latch - this interrupts the read cycle.

It seems ? 

"drives CS to low ?" CS is active low.

> We must manually keep CS in active state 

So whats active state: low or high or high-Z ?

> from third address byte latch
> to second data byte read, not during all read page cycles. And when we
> drive CS manualy - we have to disable interrupts to prevent simultaneous
> CS-s activation (NAND, PCMCIA,NOR CS).

Oh well. Disable interrupts with cli(). 

Have your Makefiles a builtin -Wignore ?


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