[PATCH] MTD NAND: Fix ECC errors in au1550nd.c

[Vitaly Bordug]

David,
This patch fixes ECC errors by automatic CS assertion in the driver.
We still use manual drive of CS only during READ CYCLE and READ OOB
CYCLE, while overriding CS right after third address byte latch and
finishing override after first data byte read.

  From the Nand read page cycle timings (Toshiba Datasheet) - we have to
keep CS active from third address byte latch to the end of the cycle.
It seems that static controller drives CS to low after fourth address
byte latch - this interrupts the read cycle.
We must manually keep CS in active state from third address byte latch
to second data byte read, not during all read page cycles. And when we
drive CS manualy - we have to disable interrupts to prevent simultaneous
CS-s activation (NAND, PCMCIA,NOR CS).

Always at your disposal for clarifications.

Signed-off-by: Konstantin Baidarov <kbaidarov at ru.mvista.com>
Signed-off-by: Vitaly Bordug <vbordug at ru.mvista.com>

-- 
Sincerely,
Vitaly


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