clean marker size for NOR w/ECC

Timofey Kutergin tkutergin at
Thu Jun 23 01:45:53 EDT 2005

I see it on modified MTDRAM simulator with added ECC write limitation (attached). Also attached is error log. With suggested modification I do not see this problem.
Patch for CFI for future chip exists and will be available at some point.


-----Original Message-----
From: Josh Boyer <jdub at>
To: Timofey Kutergin <tkutergin at>
Date: Wed, 22 Jun 2005 13:20:15 -0500
Subject: Re: Re[2]: clean marker size for NOR w/ECC

> On Wed, 2005-06-22 at 16:51 +0400, Timofey Kutergin wrote:
> > yes, I agree - eccsize is smallest write size. Or size of region which
> > can be written only once after block erase. What I meant was that if
> > eccsize is greater than cleanmarker size, JFFS2 does not skip rest of
> > first ECC region in block and tries to write data to it. This causes
> > write failure. Therefore patch sets clean marker size to eccsize if
> > eccsize is greater than 16.
> IIRC, JFFS2 will pad the node to the correct size so write failure
> shouldn't be an issue.  I could be mistaken, it's been a while.
> Is this a problem you are currently seeing, or is this all just
> theoretical?  To my knowledge, there are no other NOR ECC flash chips
> out there.  Even if there were, support would need to be added to MTD
> before they could be used.  We could adapt JFFS2 at that time if needs
> be.
> josh

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