How to exploit STS pin of Strata Flash

llandre r&d2 at
Wed Dec 29 04:00:53 EST 2004

> > To avoid the bus accesses to detect the end of erase/write operations.
> > This wastes a lot of bus bandwidth.
>I believe the current StrataFlash drivers actually sleep() for an
>appropriate amount of time in both the write and erase routines.  I'm
>not sure that they are actually going to be wasting that much useful
>bus time.  I'm curious to know if you have any data to suggest this
>bus usage has any significant impact on system performance.
> > >How?  Connect it to a irq line?
> >
> > Is this supported by MTD? How to enable this feature in the low-level 
> driver?
> > I had a look at the existing drivers but it neems no one uses interrupt ...
>No.  I was just curious what you were thinking of.  It could be done.
>If you really think its worth it.


when I helped Thomas Gleixner to debug the code to support 2k-page NAND 
devices, I
discussed with him about this subject. For NAND chips there are three 
1) if the driver can not read the ready/busy pin, MTD waits the maximum 
delay required
by the device to perform such operations (this clearly reduces performance)
2) if the driver can read the ready/busy pin, MTD polls this pin in order to
detect the end of operation (no accesses on the bus)
3) if the ready/busy ping is connected to an IRQ line, the driver can 
"sleep" until
the processor receives an interrupt from the NAND (I never implemented this 
solution so far)

I don't know how NOR/Strata Flash drivers work and I thouhgt they implement
the well-known data polling algorithm to detect the end of operation.
However, if they actually "sleeps" as you pointed out, I
clearly am wrong. If I'm right instead, the data-polling algorithm wastes 
because it performs a lot of read accesses just to read the value of a bit.
This can lead to problems for example when you have a bus-demanding 
peripheral such
as a LCD controller. In this case the wasted bandwith can lead to flickering.
In conclusion, to avoid data-polling algorithm, it is possible to implement the
same ready/busy pin strategy used for NAND chips.



DAVE Electronics System House - R&D Department
email: r&d2 at

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