DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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On Mon, 2003-03-17 at 08:40, Thayne Harbaugh wrote:
> On Wed, 2003-03-12 at 09:27, Steve Wahl wrote:

<snip>

> > I would wager you are running into the same problem I did, and that
> > your chips compatibly support DQ5, if not as a watchdog, at least by
> > holding it low while programming.
>=20
> I have sent email to PMC and the official response is that the _only_
> bits that reflect erase/write operation status are I/O7 and I/O6
> (effectively DQ7 and DQ6).  I/O7 is inverted data during the operation
> and I/O6 toggles.  The PMC response was that AMD status bits aren't
> supported.  In practice, however, DQ5 is low during erase/write
> operations.  I am uneasy about using undocumented features.

I have been thinking about the above mentioned problem with DQ5.  I have
not seen DQ5 behavior documented in the SST49LF040 and Pm49FL00x
documentation and suspect that other chip documentation is similar. =20

Regardless of the current behavior of status bit 5 on these chips I
think the documentation should be followed.  This means that either the
cfi_cmdset_0002 driver needs to be adapted to work with the "simplified"
polling in _addition_ to the current polling of DQ5 (some switch is
added to poll correctly for a given device) or a new cfi_cmdset_xxxx is
written specifically for this simplified command set.

I'm not sure what would be a nice, clean way to switch polling
mechanisms, but I hesitate to duplicate code for a nearly identical
cfi_cmdset.

Thoughts?

--=20
Thayne Harbaugh
Linux Networx

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