Handling multiple NAND chips

[J.D. Bakker]

At 11:36 -0400 25-07-2003, David Woodhouse wrote:
>On Fri, 2003-07-25 at 11:12, J.D. Bakker wrote:
>>  Hi all,
>>
>>  I have an expansion board for the LART (an embedded computer based on
>>  the DEC/Intel StrongARM) with eight NAND flash devices on it. As
>>  suggested by the Toshiba datasheet, they share data, CLE, ALE, nWE
>>  and nRE and RDY. Each chip has its own nCE line.
>>
>
>If they each had their own data/CLE/ALE etc you'd use mtdconcat. As it
>is, you want the code I've half-written to handle multiple chips in one
>MTD device.

I have a two-hour old CVS; where should I look ?

Does it *help* to have separate data/CLE/ALE ? I've read the recent 
thread on using address lines for CLE/ALE, and there's a big CPLD 
between the CPU and the NANDs, so I could make them appear to be 
separate devices. Note that all devices share the same data bus, so 
they're not attached to different byte lanes as I've seen discussed 
in the source.

Thanks again,

JDB.
[can you tell I'm a hardware guy ? ;-)]
-- 
LART. 250 MIPS under one Watt. Free hardware design files.
http://www.lart.tudelft.nl/