nand flash driver

[Charles Manning]

On Friday 11 July 2003 03:12, jasmine at regolith.co.uk wrote:
> On Thu, 10 Jul 2003, David Woodhouse wrote:
> > Hmmm. When sending multiple bytes of address, isn't ALE supposed to
> > remain high for the entire duration, without going low again between
> > cycles? How do you achieve this if it's on the address bus?
>
> By waiting to see if the next write is to the same address-  it's not hard
> to do that sort of thing in an FPGA or SoC.  Since the only line involved
> is the ALE to the NAND, there's no downside in hanging on a little longer
> before dropping it.

Certainly this will work, as would using GPIOs, FPGAs etc.

Maybe I misread the original posting, but my understanding is that the bloke 
has hardware connected to address lines. This should work, from what I read, 
although I would be more inclined to use IO pins of some sort.

Having the R/B line connected to an address line is broken for sure.

-- CHarles