nand flash driver

[jasmine at regolith.co.uk]

On Wed, 9 Jul 2003, Charles Manning wrote:

> I think most people connect CLE and ALE to GPIO pins, but some application 
> notes describe driving these via the address bus. you should then be able to 
> drive the lines the way you want by accessing the corresponding addresses.

Most people running NAND flash on general-purpose designs use GPIO lines 
to drive their ALE, CLE and to read the RNB line.  Some of these designs 
also use a GPIO to generate read and write strobes.  This is a very simple 
design to implement.

Some custom SoCs and logic-array-based implementations put all this logic 
inside the chip, decoding ALE and CLE cycles to different addresses, so 
that you write the address latch bytes to one address and the command 
latch bytes to a different one.  This is slightly neater, though can have 
complications with interrupt latency (requirement to stretch read and 
write cycles to some parts of the address map, etc.)

Some devices take all this stuff and put it inside a piece of logic that 
manages a pipeline of bytes in and out of the NAND.  Some SoCs do this, 
and of course DiskOnChip does something like this, resolving NAND access 
into cycles that look like conventional NOR or ROM cycles.  This is, in 
some ways, the easiest to implement, though it seems to have caused MTD 
the most problems, though that is mostly because of M-Systems' intentional 
obfuscation tactics.

-Jas.