nand flash driver

[Charles Manning]

On Monday 07 July 2003 14:33, gjx wrote:
> hi,linux-mtd
>
> 	 The hardware designer connects the control pins(CLE¡¢ALE¡¢R/B) of nand
> flash to the data bus, The CE¡¢WE¡¢RE pins to corresponding pin of CPU.
> Nedd I get the address of control pins? separate the data from data bus?
> How to implement controlling of nand.   Please give me some advice, thanks!

R/B is an open collector that is driven from the NAND. You should not be 
connecting this to the address bus. You can just leave this unconnected (R/B 
detection not available) or connect it to a GPIO.

I think most people connect CLE and ALE to GPIO pins, but some application 
notes describe driving these via the address bus. you should then be able to 
drive the lines the way you want by accessing the corresponding addresses.

-- CHarles