Oh, the many joys of MTD...

Robert Kaiser rob at sysgo.de
Mon Mar 12 05:10:44 EST 2001

On Don, 08 Mär 2001 you wrote:
> >
> > The device mapping is done with the ioremap() call which is responsible for
> > providing a non-cacheable mapping.
> Actually I had to use ioremap_nocache() call with my ELANSC520 processor (which
> has a processor I&D cache).

Strange, I had just the opposite experience here. I'm using the SC520 CDP board.

> This is even with caching actually disabled for the flash banks inside the
> processor (by the startup processor init code).

My board's BIOS provides options to enable/disable write buffering and to
set cache operation to write-back/write-through. No matter how I set these,
the mtd code always seemed to work, even if I used plain ioremap() . The SC520
has a set of PAR registers which allow to set individual cachability attributes
for ROM (i.e. chips that are selected by the ROMCS[12] and BOOTCS signals).
These are always set to non-cacheable by my BIOS. Then there are also the
cacheability attributes in the page table (this is what ioremap()  and
ioremap_nocache() differ in).

So there are several obscure places where one can enable/disable cacheing for
a given address region  on an SC520. Question is which of them takes
precedence in case they contradict.

Nevertheless, since everybody seems to agree that FlashROM needs to be
non-cached for the MTD code to work, I guess it's safer to generally use


Robert Kaiser                         email: rkaiser at sysgo.de
Am Pfaffenstein 14                    phone: (49) 6136 9948-762
D-55270 Klein-Winternheim / Germany   fax:   (49) 6136 9948-10

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