mtd: spi-nor: support dual, quad, and WP for Gigadevice

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=595f0e101d4c250010ca0763ae15b863f01bb90e
Commit:     595f0e101d4c250010ca0763ae15b863f01bb90e
Parent:     cebc1fd0690713ec86ab27e606daf9967a2833ab
Author:     Brian Norris <computersforpeace at gmail.com>
AuthorDate: Fri Jul 1 15:16:22 2016 -0700
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Wed Jul 13 17:36:01 2016 -0700

    mtd: spi-nor: support dual, quad, and WP for Gigadevice
    
    Gigadevice flash support BP{0,1,2,3,4} bits, where BP3 means the same as
    the existing supported TB (Top/Bottom), and BP4 means the same as the
    not-yet-supported 4K bit used on other flash (e.g., Winbond). Let's
    support lock/unlock with the same feature flags as w25q32dw/w25q64dw.
    
    Tested on gd25lq64c, but I checked datasheets for the other 3, to make
    sure.
    
    While I was at it, I noticed that these all support dual and quad as
    well. I noted them, but can't test them at the moment, since my test
    system only supports standard 1x SPI.
    
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index ddce5fd..d0fc165 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -830,10 +830,26 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
 
 	/* GigaDevice */
-	{ "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64, SECT_4K) },
-	{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
-	{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-	{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
+	{
+		"gd25q32", INFO(0xc84016, 0, 64 * 1024,  64,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
+	{
+		"gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
+	{
+		"gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
+	{
+		"gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
 
 	/* Intel/Numonyx -- xxxs33b */
 	{ "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },