mtd: nand: lpc32xx_slc: fix calculation of timing arcs from given values

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=d54e88011d0a5fb48d9bb60fede3e83375c75841
Commit:     d54e88011d0a5fb48d9bb60fede3e83375c75841
Parent:     08d3cd5ef0633df84d119e939d8d1b56c6e4a5e7
Author:     Vladimir Zapolskiy <vz at mleia.com>
AuthorDate: Thu Oct 1 02:23:37 2015 +0300
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Sun Oct 4 22:30:49 2015 +0100

    mtd: nand: lpc32xx_slc: fix calculation of timing arcs from given values
    
    According to LPC32xx User's Manual all values measured in clock cycles
    are programmable from 1 to 16 clocks (4 bits) starting from 0 in
    bitfield, the current version of calculated clock cycles is too
    conservative.
    
    Correctness of 0 bitfield value (i.e. programmed 1 clock
    timing) is proven with actual NAND chip devices.
    
    Signed-off-by: Vladimir Zapolskiy <vz at mleia.com>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/lpc32xx_slc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c
index a9e8a02..cbf4501 100644
--- a/drivers/mtd/nand/lpc32xx_slc.c
+++ b/drivers/mtd/nand/lpc32xx_slc.c
@@ -95,7 +95,7 @@
 * slc_tac register definitions
 **********************************************************************/
 /* Computation of clock cycles on basis of controller and device clock rates */
-#define SLCTAC_CLOCKS(c, n, s)	(min_t(u32, 1 + (c / n), 0xF) << s)
+#define SLCTAC_CLOCKS(c, n, s)	(min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
 
 /* Clock setting for RDY write sample wait time in 2*n clocks */
 #define SLCTAC_WDR(n)		(((n) & 0xF) << 28)