mtd: nand: lpc32xx_slc: fix potential overflow over 4 bits

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Gitweb:     http://git.infradead.org/?p=mtd-2.6.git;a=commit;h=08d3cd5ef0633df84d119e939d8d1b56c6e4a5e7
Commit:     08d3cd5ef0633df84d119e939d8d1b56c6e4a5e7
Parent:     641f6342f507cfe671ac5a58768a8473e14ae2ac
Author:     Vladimir Zapolskiy <vz at mleia.com>
AuthorDate: Thu Oct 1 02:23:36 2015 +0300
Committer:  Brian Norris <computersforpeace at gmail.com>
CommitDate: Sun Oct 4 22:30:49 2015 +0100

    mtd: nand: lpc32xx_slc: fix potential overflow over 4 bits
    
    In case if quotient of controller clock rate to device clock rate does
    not fit into 4 bit value, choose the maximum acceptable value 0xF, which
    stands for 16 clocks.
    
    Signed-off-by: Vladimir Zapolskiy <vz at mleia.com>
    Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/lpc32xx_slc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c
index 9ac0f3b..a9e8a02 100644
--- a/drivers/mtd/nand/lpc32xx_slc.c
+++ b/drivers/mtd/nand/lpc32xx_slc.c
@@ -95,7 +95,7 @@
 * slc_tac register definitions
 **********************************************************************/
 /* Computation of clock cycles on basis of controller and device clock rates */
-#define SLCTAC_CLOCKS(c, n, s)	(((1 + (c / n)) & 0xF) << s)
+#define SLCTAC_CLOCKS(c, n, s)	(min_t(u32, 1 + (c / n), 0xF) << s)
 
 /* Clock setting for RDY write sample wait time in 2*n clocks */
 #define SLCTAC_WDR(n)		(((n) & 0xF) << 28)