mtd/drivers/mtd/maps dc21285.c,1.16,1.17

[gleixner at infradead.org]

Update of /home/cvs/mtd/drivers/mtd/maps
In directory phoenix.infradead.org:/tmp/cvs-serv30734

Modified Files:
	dc21285.c 
Log Message:
Fix it really

Index: dc21285.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/maps/dc21285.c,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -r1.16 -r1.17
--- dc21285.c	15 Apr 2004 21:05:33 -0000	1.16
+++ dc21285.c	15 Apr 2004 21:50:26 -0000	1.17
@@ -75,7 +75,8 @@
 
 void dc21285_write8(struct map_info *map, __u8 d, unsigned long adr)
 {
-	nw_en_write();
+	if (machine_is_netwinder())
+		nw_en_write();
 	*CSR_ROMWRITEREG = adr & 3;
 	adr &= ~3;
 	*(__u8*)(map->map_priv_1 + adr) = d;
@@ -83,7 +84,8 @@
 
 void dc21285_write16(struct map_info *map, __u16 d, unsigned long adr)
 {
-	nw_en_write();
+	if (machine_is_netwinder())
+		nw_en_write();
 	*CSR_ROMWRITEREG = adr & 3;
 	adr &= ~3;
 	*(__u16*)(map->map_priv_1 + adr) = d;
@@ -91,7 +93,8 @@
 
 void dc21285_write32(struct map_info *map, __u32 d, unsigned long adr)
 {
-	nw_en_write();
+	if (machine_is_netwinder())
+		nw_en_write();
 	*(__u32*)(map->map_priv_1 + adr) = d;
 }
 
@@ -149,20 +152,9 @@
 int __init init_dc21285(void)
 {
 
-	if(machine_is_ebsa285()) {
-		/* 
-		 * Flash timing is determined with bits 19-16 of the
-		 * CSR_SA110_CNTL.  The value is the number of wait cycles, or
-		 * 0 for 16 cycles (the default).  Cycles are 20 ns.
-		 * Here we use 7 for 140 ns flash chips.
-		 */
-		/* access time */
-		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16));
-		/* burst time */
-		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20));
-		/* tristate time */
-		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24));
-	}	
+#ifdef CONFIG_MTD_PARTITIONS
+	int nrparts;
+#endif
 
 	/* Determine buswidth */
 	switch (*CSR_SA110_CNTL & (3<<14)) {
@@ -195,25 +187,37 @@
 		dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map);
 	}
 
-	if (dc21285_mtd) {
+	if (!dc21285_mtd) {
+		iounmap((void *)dc21285_map.map_priv_1);
+		return -ENXIO;
+	}	
 	
+	dc21285_mtd->owner = THIS_MODULE;
+
 #ifdef CONFIG_MTD_PARTITIONS
-		int nrparts;
-		dc21285_mtd->owner = THIS_MODULE;
-		nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, (void *)0);
-		if (nrparts > 0) {
-			add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts);
-			return 0;
-		}
-#else		
-		dc21285_mtd->owner = THIS_MODULE;
-#endif
+	nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, (void *)0);
+	if (nrparts > 0)
+		add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts);
+	else	
+#endif	
 		add_mtd_device(dc21285_mtd);
-		return 0;
-	}
 			
-	iounmap((void *)dc21285_map.map_priv_1);
-	return -ENXIO;
+	if(machine_is_ebsa285()) {
+		/* 
+		 * Flash timing is determined with bits 19-16 of the
+		 * CSR_SA110_CNTL.  The value is the number of wait cycles, or
+		 * 0 for 16 cycles (the default).  Cycles are 20 ns.
+		 * Here we use 7 for 140 ns flash chips.
+		 */
+		/* access time */
+		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16));
+		/* burst time */
+		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20));
+		/* tristate time */
+		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24));
+	}
+	
+	return 0;
 }
 
 static void __exit cleanup_dc21285(void)