mtd/drivers/mtd/maps dc21285.c,1.15,1.16

[gleixner at infradead.org]

Update of /home/cvs/mtd/drivers/mtd/maps
In directory phoenix.infradead.org:/tmp/cvs-serv30203

Modified Files:
	dc21285.c 
Log Message:
fix machine dependencies. Patch provided by Vincent Sanders

Index: dc21285.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/maps/dc21285.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -r1.15 -r1.16
--- dc21285.c	21 May 2003 12:45:18 -0000	1.15
+++ dc21285.c	15 Apr 2004 21:05:33 -0000	1.16
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/delay.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
@@ -19,9 +20,38 @@
 
 #include <asm/io.h>
 #include <asm/hardware/dec21285.h>
+#include <asm/mach-types.h>
 
 
-static struct mtd_info *mymtd;
+static struct mtd_info *dc21285_mtd;
+
+#ifdef CONFIG_ARCH_NETWINDER
+/* 
+ * This is really ugly, but it seams to be the only
+ * realiable way to do it, as the cpld state machine 
+ * is unpredictible. So we have a 25us penalty per
+ * write access.
+ */
+static void nw_en_write(void) {
+	extern spinlock_t gpio_lock;
+	unsigned long flags;
+
+	/*
+	 * we want to write a bit pattern XXX1 to Xilinx to enable
+	 * the write gate, which will be open for about the next 2ms.
+	 */
+	spin_lock_irqsave(&gpio_lock, flags);
+	cpld_modify(1, 1);
+	spin_unlock_irqrestore(&gpio_lock, flags);
+
+	/*
+	 * let the ISA bus to catch on...
+	 */
+	udelay(25);
+}
+#else
+#define nw_en_write()
+#endif
 
 __u8 dc21285_read8(struct map_info *map, unsigned long ofs)
 {
@@ -45,6 +75,7 @@
 
 void dc21285_write8(struct map_info *map, __u8 d, unsigned long adr)
 {
+	nw_en_write();
 	*CSR_ROMWRITEREG = adr & 3;
 	adr &= ~3;
 	*(__u8*)(map->map_priv_1 + adr) = d;
@@ -52,6 +83,7 @@
 
 void dc21285_write16(struct map_info *map, __u16 d, unsigned long adr)
 {
+	nw_en_write();
 	*CSR_ROMWRITEREG = adr & 3;
 	adr &= ~3;
 	*(__u16*)(map->map_priv_1 + adr) = d;
@@ -59,6 +91,7 @@
 
 void dc21285_write32(struct map_info *map, __u32 d, unsigned long adr)
 {
+	nw_en_write();
 	*(__u32*)(map->map_priv_1 + adr) = d;
 }
 
@@ -116,18 +149,20 @@
 int __init init_dc21285(void)
 {
 
-	/* 
-	 * Flash timing is determined with bits 19-16 of the
-	 * CSR_SA110_CNTL.  The value is the number of wait cycles, or
-	 * 0 for 16 cycles (the default).  Cycles are 20 ns.
-	 * Here we use 7 for 140 ns flash chips.
-	 */
-	/* access time */
-	*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16));
-	/* burst time */
-	*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20));
-	/* tristate time */
-	*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24));
+	if(machine_is_ebsa285()) {
+		/* 
+		 * Flash timing is determined with bits 19-16 of the
+		 * CSR_SA110_CNTL.  The value is the number of wait cycles, or
+		 * 0 for 16 cycles (the default).  Cycles are 20 ns.
+		 * Here we use 7 for 140 ns flash chips.
+		 */
+		/* access time */
+		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16));
+		/* burst time */
+		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20));
+		/* tristate time */
+		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24));
+	}	
 
 	/* Determine buswidth */
 	switch (*CSR_SA110_CNTL & (3<<14)) {
@@ -154,25 +189,29 @@
 		return -EIO;
 	}
 
-	mymtd = do_map_probe("cfi_probe", &dc21285_map);
-	if (mymtd) {
-		int nrparts = 0;
-
-		mymtd->owner = THIS_MODULE;
-			
-		/* partition fixup */
+	if (machine_is_ebsa285()) {
+		dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map);
+	} else {
+		dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map);
+	}
 
+	if (dc21285_mtd) {
+	
 #ifdef CONFIG_MTD_PARTITIONS
-		nrparts = parse_mtd_partitions(mymtd, probes, &dc21285_parts, (void *)0);
+		int nrparts;
+		dc21285_mtd->owner = THIS_MODULE;
+		nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, (void *)0);
 		if (nrparts > 0) {
-			add_mtd_partitions(mymtd, dc21285_parts, nrparts);
+			add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts);
 			return 0;
 		}
+#else		
+		dc21285_mtd->owner = THIS_MODULE;
 #endif
-		add_mtd_device(mymtd);
+		add_mtd_device(dc21285_mtd);
 		return 0;
 	}
-
+			
 	iounmap((void *)dc21285_map.map_priv_1);
 	return -ENXIO;
 }
@@ -181,13 +220,13 @@
 {
 #ifdef CONFIG_MTD_PARTITIONS
 	if (dc21285_parts) {
-		del_mtd_partitions(mymtd);
+		del_mtd_partitions(dc21285_mtd);
 		kfree(dc21285_parts);
 	} else
 #endif
-		del_mtd_device(mymtd);
+		del_mtd_device(dc21285_mtd);
 
-	map_destroy(mymtd);
+	map_destroy(dc21285_mtd);
 	iounmap((void *)dc21285_map.map_priv_1);
 }