[PATCH v2 8/8] PCI: rzg3s-host: Add 100 ms delay after link training

[Hans Zhang]

On 5/7/26 00:52, Claudiu Beznea wrote:
> Hi, Hans,
> 
> On 5/6/26 18:23, Hans Zhang wrote:
>> The Renesas RZ/G3S PCIe host driver currently does not enforce the
>> mandatory 100 ms delay after link training completes for speeds > 5.0 
>> GT/s,
>> required by PCIe r6.0 sec 6.6.1.
>>
>> The driver already has a 'max_link_speed' field (derived from the device
>> tree). Add a call to pcie_wait_after_link_train() in
>> rzg3s_pcie_host_init() after reading the link status, ensuring that the
>> delay is applied before any Configuration Request is sent downstream.
>>
>> Signed-off-by: Hans Zhang <18255117159 at 163.com>
>> ---
>>   drivers/pci/controller/pcie-rzg3s-host.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/ 
>> controller/pcie-rzg3s-host.c
>> index d86e7516dcc2..6ab59c5464cf 100644
>> --- a/drivers/pci/controller/pcie-rzg3s-host.c
>> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
>> @@ -1390,6 +1390,8 @@ static int rzg3s_pcie_host_init(struct 
>> rzg3s_pcie_host *host)
>>       val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
>>       dev_info(host->dev, "PCIe link status [0x%x]\n", val);
>> +    pcie_wait_after_link_train(host->max_link_speed);
> 
> There is an msleep(PCIE_RESET_CONFIG_WAIT_MS) after 
> rzg3s_pcie_set_max_link_speed() call. Shouldn't that msleep() call be 
> replaced with your pcie_wait_after_link_train() ?

Hi Claudiu,

Sorry for the late reply. Thank you for pointing it out. It will be 
replaced.

Best regards,
Hans


> 
> Thank you,
> Claudiu