[PATCH v2 3/3] mips: dts: ralink: mt7621: add serial1 and serial2 nodes
Arınç ÜNAL
arinc.unal at arinc9.com
Fri Mar 8 05:50:56 PST 2024
On 7.03.2024 22:04, Justin Swartz wrote:
> Add serial1 and serial2 nodes to define the existence of
> the MT7621's second and third UARTs.
>
> Signed-off-by: Justin Swartz <justin.swartz at risingedge.co.za>
> ---
> arch/mips/boot/dts/ralink/mt7621.dtsi | 28 +++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
> index 3ad4e2343..5a89f0b8c 100644
> --- a/arch/mips/boot/dts/ralink/mt7621.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
> @@ -124,6 +124,34 @@ serial0: serial at c00 {
> pinctrl-0 = <&uart1_pins>;
> };
>
> + serial1: serial at d00 {
> + compatible = "ns16550a";
> + reg = <0xd00 0x100>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + clocks = <&sysc MT7621_CLK_UART2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
> + no-loopback-test;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pins>;
> + status = "disabled";
> + };
I would group this:
serial1: serial at d00 {
compatible = "ns16550a";
reg = <0xd00 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&sysc MT7621_CLK_UART2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
Same goes for patch 2.
Arınç
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